1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register capable of self-feedback.
2. Description of the Prior Art
A liquid crystal display (LCD) is a flat screen display panel that is manufactured from a glass base. A future trend of manufacturing an LCD will be by driving a control circuit that uses a thin film transistor (TFT) technology to make the glass base of the LCD whereas the current method of production utilizes an amorphous silicon layer that is far less suitable for producing high-grade transistors.
Please refer to FIG. 1 through to FIG. 3. FIG. 1 illustrates a diagram of a conventional LCD 100. FIG. 2 illustrates a diagram of a gate driving circuit 120 of the LCD 100 of FIG. 1. FIG. 3 illustrates a diagram of a shift register of the gate driving circuit 120 of FIG. 2. As illustrated in the figures, the LCD 100 includes a display array 110, and a gate driving circuit 120. The display array 110 is utilized for displaying images, and the gate driving circuit 120 is utilized for driving the display array 110. The gate driving circuit 120 includes a plurality of stage shift registers 122, the stage shift registers 122 are electrically coupled in a series connection and a gate signal GOUT is generated to drive the display array 110 in response to a first clock signal CK and a second clock signal XCK sequentially. The phase of the second clock signal XCK is opposite to the phase of the first clock signal CK. Regarding the connection of each stage shift register 122, the first clock signal CK and the second clock signal XCK alternately exchange information, which means that a clock signal input end CK1 and a clock signal input end CK2 is alternately coupled to the first clock signal CK and the second clock signal XCK. Each stage shift register 122 has an output end OUT, an input end IN, and a feedback end FB. The stage shift register 122 includes a signal generating circuit 310, a driving circuit 320, a primary reset circuit 330, and two secondary reset circuits 340, 350. As illustrated in FIG. 3, the signal generating circuit 310 is utilized for generating a gate signal GOUT(N) at the output end OUT of the shift register 122 in response to the first clock signal CK (which can also be the second clock signal XCK) while the signal generating circuit 310 is being turned on. The driving circuit 320 is utilized for controlling the signal generating circuit 310 in response to the input signal received by the input end IN of the shift register 122. The input signal received by the input end IN of the shift register 122 is the gate signal GOUT(N−1) from a previous stage shift register. The primary reset circuit 330 is utilized for turning off the signal generating circuit 310 and resetting the gate signal GOUT(N) from the output end OUT (which means that voltage of the output end is being lowered to a predetermined low electrical potential VSS), and feedback signal transmitted by the feedback end FB is a gate signal GOUT(N+1) from an output end of a previous stage shift register. The secondary reset circuits 340, 350 are utilized for alternately turning off the signal generating circuit 310 and resetting the output signal of the output end OUT in response to the first clock signal CK and the second clock signal XCK.
Although the functions of the secondary reset circuits 340, 350 and the primary reset circuit 330 are quite similar, the primary reset circuit 330 differs from the secondary reset circuits 340, 350 in that it only operates after receiving a gate signal GOUT(N+1) from a next stage shift register. The secondary reset circuits 340, 350 operate continuously for long period of time. When the TFT is in operation for a long period of time, then efficient can reduced as well as its lifespan. Therefore, the primary reset circuit 330 is only operated once every operation cycle, thus noise interference can be prevented thereby prolonging the operation lifespan of the product.
To further explain the operation of the conventional shift register 122 in detail, please refer to FIG. 4 and at the same time to FIG. 3. FIG. 4 illustrates a clock diagram of each related signal of the shift register 122 of FIG. 3 during operation. As illustrated in FIG. 4, in time T1, the input signal (which can be the gate signal GOUT(N−1) or a start signal (ST) from the output end of the previous stage shift register) is being raised to a high electrical potential, hence thin film transistor (TFT) TFT1 of the driving circuit 320 is initialized, which causes the signal generating circuit 310 to initialize as well. However, the first clock signal CK at T1 is at low electrical potential, the gate signal GOUT(N) from the output end OUT remains in a low electrical potential, furthermore because the feedback signal GOUT (N+1) of the feedback end FB is at low electrical potential the primary reset circuit 330 does not operate at point N4 because electrical potential is low, because the first clock signal CK is at low electrical potential the secondary reset circuit 340 does not operate at point N2 because electrical potential is low, and because the input signal GOUT(N−1) or ST turns on TFT8 at T1 the secondary reset circuit 350 does not operate at point N3 because electrical potential is low.
At time T2, the input signal GOUT(N−1) or ST received by the input end IN is being lowered to low electrical potential, thus TFT1 of the driving circuit 320 is turned off, however the signal generating circuit 310 is still turned on, electrical potential is raised to high electrical potential at N1 due to electric capacitance on the first clock signal CK when the first clock signal CK is raised to high electrical potential, and the gate signal GOUT(N) from the output end OUT also becomes high electrical potential. Furthermore, because TFT15 is turned on by the first clock signal CK at T2 the primary reset circuit 330 does not operate at point N4 because electrical potential is low, because TFT11 is turned on by the gate signal GOUT(N) from the output end OUT at T2 the secondary reset circuit 340 does not operate at point N2 because electrical potential is low, and because the second clock signal XCK is at low electrical potential the secondary reset circuit 350 does not operate at point N3 because electrical potential is low.
At time T3, the primary reset circuit 330 turns on TFT16, TFT17, and turns off the signal generating circuit 310 (N1 is at low electrical potential) and lowers the gate signal GOUT(N) from the output end OUT into low electrical potential, because the second clock signal XCK turns on TFT14 and the feedback signal GOUT(N+1) of the feedback end FB rises to high electrical potential which directly causes point N4 to be high electrical potential. Furthermore, because the first clock signal CK is at low electrical potential the secondary reset circuit 340 does not operate at point N2 because electrical potential is low, however because the second clock signal XCK is at high electrical potential the secondary reset circuit 350 at point N3 is at high electrical potential) and at the same time TFT3, TFT6 are being turned on, the signal generating circuit 310 is being turned off, and the gate signal GOUT(N) from the output end OUT is being lowered to low electrical potential.
Within other following time, the secondary reset circuit 340 and the secondary reset circuit 350 will operate alternately to turn off the signal generating circuit 310 and lower the gate signal GOUT(N) from the output end to low electrical potential until the input signal GOUT(N−1) of the input end IN or ST is again raised to high electrical potential. Also, a next stage shift register 122 will repeat the above-mentioned actions, thus the gate signal GOUT can be sequentially generated to drive the display array 10.
However, the gate signal GOUT from each stage shift register 122 is not only utilized for driving the display array, but also utilized for outputting to an input end IN of a next stage shift register 122 and a feedback end FB of a previous stage shift register 122, therefore the work load of the output end OUT is increased. This action also results in increasing the rising time and falling time of the gate signal GOUT from each stage shift register 122. Furthermore, a feedback end FB of a last stage shift register of the gate driving circuit 120 is unable to receive a feedback signal thus causing a primary reset circuit 330 of the last state shift circuit 122 to stop operating, which results in shortening of the operation life span of the last stage shift register 122 that can cause damage on the gate driving circuit 120.